M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 237

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.5.23
This register, in conjunction with the IMA_RX_GRPn_CTL and IMA_RX_GRPn_CFG registers, controls the
operation of the Receive IMA group.
Group 1–16 Address
Group 17–32 Address
28529-DSH-001-K
n=17
0x8D
0xC5
n=1
4–0
2
2
Bit
7
6
5
n=18
0x8D
0xC5
n=2
6
6
Default
0x00
0
0
0
0x8DA
n=19
0xC5
n=3
A
IMA_RX_GRPn_FIRST_PHY_ADDR (Receive First PHY Address)
Resync Group
Drain Buffer
Rx IMA Version
Link PHY Address
0xC5E
n=20
0x8DE
n=4
Name
n=21
0xCD
0x9D
n=5
2
2
n=22
0xCD
Mindspeed Proprietary and Confidential
0x9D
Mindspeed Technologies
n=6
6
6
1 = Enables the link differential delay synchronization process
0 = Disables the link differential delay synchronization process
This bit is used by the software driver to reset the differential delay in T1/E1 mode:
IMA OAM Label value
This field contains the PHY port address of the Receive link with the lowest LID in the group.
1 = IMA v1.1
0 = IMA v1.0
M28525: Range: 0–0xF
M28529: Range: 0–0x1F
1 = Allows the differential delay buffer to drain excess cell buffering.
0 = Normal delay buffering.
0x9DA
n=23
0xCD
n=7
A
M28525 -- Not Applicable
0x9DE
n=24
0xCD
n=8
E
M28525
M28529
M28529
n=25
0xD5
0xAD
n=9
2
2
n=26
0xD5
n=10
0xAD
6
6
®
Description
0xADA
n=27
0xD5
n=11
A
0xD5E
n=28
n=12
0xAD
E
n=29
0xDD
n=13
0xBD
2
2
n=30
0xDD
n=14
0xBD
6
6
0xBDA
n=31
n=15
0xDD
Registers
A
n=16
n=32
0xDD
0xBD
E
E
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