M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 113

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Figure 1-32. Fractional T1 Timing.
Figure 1-33
and the sync inputs are used to indicate active data timeslots. The clocks are gapped internally in the M28525/9
during inactive timeslots. ATM cell bytes are continuously mapped into active timeslots.
Figure 1-33. Fractional E1 Timing.
1.14.2.5.3
In DSL mode, the clock frequency can be up to 8.192 MHz. On the receive side, the sync input signals tell the TC
Port receiver to ignore the corresponding bits on the data bus. This can be used to mask out overhead bits. Other
than such overhead bits, the receive data stream should contain only serialized ATM cells. On the transmit side,
sync is an output and is used to indicate the start of cell – the MSB of the first byte of the cell. Only serialized ATM
data cells are present in the transmit data stream
The M2852x has a DSL mode interface as illustrated in
require frame synchronization. The M2852x receives a data stream from the external framer, performs bit level cell
28529-DSH-001-K
sprxclk (2.048 MHz)
sptxclk (2.048 MHz)
sprxclk (1.544 MHz)
sptxclk (1.544 MHz)
shows an example of fractional E1 timing. In Fractional E1 mode, the clock frequency is 2.048 MHz,
sprxsync
sprxdata
sptxsync
sptxdata
sprxsync
sprxdata
sptxsync
sptxdata
NOTE:
DSL Mode Interface
TS31
TS31
TS24
TS24
To enable fractional T1/E1 on a link, the appropriate EnFrac bits must be set in the TC
Control Registers, (TCCTRL0-TCCTRL7). The PhyType[2:0] bits in the Port Mode Control
register for the link should also be configured to be in xDSL framing mode (PMODE[2:0] =
110). CGEN[3] (DSLSyncPol) must also be set to 1.
F
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TS0 (overhead)
TS1
Figure
TS1 (inactive)
1-34. This mode allows connection with framers that
TS1
®
TS2 (inactive)
TS2
Functional Description
TS2
TS3
TS3
TS3
TS3
98