M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 187

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.2.40
The RXCELLINT register indicates that a change of status has occurred within the receive status signals.
2.2.41
The TXCELL register contains status for the cell transmitter. This register is cleared on read. Bits 1-7 are read-
only.
28529-DSH-001-K
Footnote:
(1) Single event—A 0 to 1 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt has been
(2) Dual event—Either a 0 to 1 or a 1 to 0 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt
Footnote:
(1) This status indicates an event that occurred since the register was last read.
Bit
Bit
enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
has been enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0x2D—RXCELLINT (Receive Cell Interrupt Indication Status Register)
0x2E—TXCELL (Transmit Cell Status Register)
LOCDInt
HECDetInt
HECCorrInt
CellRcvdInt
IdleRcvdInt
NonMatchInt
NonZerGFCInt
ParErr
SOCErr
TxOvfl
RxOvfl
CellSent
(1)
(1)
(1)
(1)
(1)
(2)
Name
Name
(1)
—
—
—
—
(1)
(1)
(1)
(1)
(1)
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When a logical 1 is read, this bit indicates that a Loss of Cell Delineation has occurred.
When a logical 1 is read, this bit indicates that a HEC Error was detected.
Reserved, write to a logical 0.
When a logical 1 is read, this bit indicates that a cell has been received.
When a logical 1 is read, this bit indicates that an Idle Cell has been received.
When a logical 1 is read, this bit indicates that a Non-matching Cell has been received.
When a logic 1 is read, this bit indicates that a Non-zero GFC has been received.
When a logical 1 is read, this bit indicates that a parity error was received on the transmit
UTOPIA input data octet.
When a logical 1 is read, this bit indicates that a Start of Cell Error was received on the UTxSOC
pin (pin TBD).
When a logical 1 is read, this bit indicates that a Transmit FIFO Overflow condition occurred in
the transmit UTOPIA FIFO.
When a logical 1 is read, this bit indicates that a Receive FIFO Overflow condition occurred in the
receive UTOPIA FIFO.
When a logical 1 is read, this bit indicates that a non-idle cell was formatted and transmitted.
Reserved for factory test, ignore.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
When a logical 1 is read, this bit indicates that a HEC Error was corrected.
®
Description
Description
Registers
172