ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 106
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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8285D–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 15-3.
Table 15-4
mode.
Table 15-4.
Note:
Table 15-5
rect PWM mode.
Table 15-5.
Note:
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
COM0A1
COM0A1
COM0A1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at BOTTOM. See
page 100
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
pare match is ignored, but the set or clear is done at TOP. See
page 101
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM0A0
COM0A0
COM0A0
for more details.
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
Table 15-3
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when down counting.
Set OC0A on compare match when up-counting. Clear OC0A on
compare match when down counting.
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match, set OC0A at BOTTOM
(non-inverting mode)
Set OC0A on compare match, clear OC0A at BOTTOM
(inverting mode)
shows the COM0A1:0 bit functionality when the WGM01:0 bits
(1)
(1)
”Phase Correct PWM Mode” on
”Fast PWM Mode” on
106
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