ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 50
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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11.3
11.3.1
11.4
8285D–AVR–06/11
Internal Voltage Reference
Watchdog Timer
Voltage Reference Enable Signals and Start-up Time
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P features an inter-
nal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an
input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2...0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P resets and exe-
cutes from the Reset Vector. For timing details on the Watchdog Reset, refer to
page
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 11-1. Refer to
”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 51
details.
Table 11-1.
WDTON
Unprogrammed
Programmed
ACBG bit in ACSR).
54.
Table 11-2 on page
WDT Configuration as a Function of the Fuse Settings of WDTON
CC
Safety
Level
= 5V. See characterization data for typical values at other V
1
2
”System and Reset Characteristics” on page
54. The WDR – Watchdog Reset – instruction resets the Watch-
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
326. To save power, the
How to Change Time-
out
Timed sequence
Timed sequence
Table 11-2 on
CC
levels. By
for
50
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