ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 181
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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20.7.2
8285D–AVR–06/11
Receiving Frames with 9 Data Bits
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8n bit in UCSRnB
before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Sta-
tus Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O
location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn,
DORn and UPEn bits, which all are stored in the FIFO, will change.
The following code example shows a simple USART receive function that handles both nine bit
characters and the status bits.
181
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