ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 35
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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9.7
8285D–AVR–06/11
External Clock
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
To drive the device from an external clock source, XTAL1 should be driven as shown in
9-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 9-3.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 9-12.
Table 9-13.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to
36
ATmega 165A/165PA/645A/645P
ATmega325A/325PA/3250A/3250PA/6450A/6450P
SUT1..0
for details.
00
01
10
11
9-13.
Start-up Time from Power-
External Clock Drive Configuration
Crystal Oscillator Clock Frequency
Start-up Times for the External Clock Selection
down and Power-save
6 CK
6 CK
6 CK
EXTERNAL
SIGNAL
CLOCK
NC
Additional Delay from
Reset (V
Reserved
14CK + 4.1ms
14CK + 65ms
14CK
XTAL2
XTAL1
GND
CC
CKSEL3...0
0000
0000
= 5.0V)
”System Clock Prescaler” on page
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
Frequency Range
0 - 16MHz
0 - 20MHz
Figure
35
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