ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 15
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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7.6.1
7.7
8285D–AVR–06/11
Instruction Execution Timing
SPH and SPL – Stack Pointer
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 7-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 7-4.
Figure 7-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 7-5.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
R/W
R/W
SP7
15
–
7
0
0
clk
clk
CPU
CPU
SP6
R/W
R/W
14
–
6
0
0
SP5
R/W
R/W
CPU
13
–
5
0
0
T1
T1
, directly generated from the selected clock source for the
SP4
R/W
R/W
12
–
4
0
0
T2
SP3
R/W
R/W
T2
11
–
3
0
0
SP10
SP2
R/W
R/W
10
2
0
0
T3
T3
SP9
SP1
R/W
R/W
9
1
0
0
R/W
R/W
SP8
SP0
8
0
0
0
T4
T4
SPH
SPL
15
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