ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 64
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.2
13.2.1
13.2.2
8285D–AVR–06/11
Register Description
EICRA – External Interrupt Control Register A
EIMSK – External Interrupt Mask Register
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 13-1.
• Bit 7 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT30:24 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3
Interrupt Vector. PCINT30:24 pins are enabled individually by the PCMSK3 Register.
Note:
• Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT2
Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.
Note:
Bit
(0x69)
Read/Write
Initial Value
Bit
0x1D (0x3D)
Read/Write
Initial Value
ISC01
0
0
1
1
1. This bit is a reserved bit in
1. This bit is a reserved bit in
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and
should always be written to zero.
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and
should always be written to zero.
Interrupt 0 Sense Control
PCIE3
ISC00
R
7
–
0
R
7
0
0
1
0
1
(1)
PCIE2
Table
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R
6
–
0
R
6
0
(1)
13-1. The value on the INT0 pin is sampled before detecting
PCIE1
R/W
R
5
–
0
5
0
PCIE0
R/W
R
4
–
0
4
0
R
3
–
0
R
3
–
0
R
2
–
0
2
–
R
0
ISC01
R/W
1
0
R
1
–
0
ISC00
R/W
INT0
R/W
0
0
0
0
EICRA
EIMSK
64
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