ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 204
ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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8285D–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Figure 21-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram
steps:
1. The a start condition is generated by the Master by forcing the SDA low line while the
2. In addition, the start detector will hold the SCL line low after the Master has forced an
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
4. After eight bits are transferred containing slave address and data direction (read or
5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given
If the Slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the Master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 21-6. Start Condition Detector, Logic Diagram
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the corresponding bit in the PORT Register to zero. Note that the
Data Direction Register bit must be set to one for the output to be enabled. The slave
device’s start detector logic
sets the USISIF Flag. The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the Slave to wake up from sleep or complete
its other tasks before setting up the Shift Register to receive the address. This is done by
clearing the start condition flag and reset the counter.
samples the data and shift it into the Serial Register at the positive edge of the SCL
clock.
write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the Master has addressed, it releases the SCL line and waits for a new start
condition.
before holding the SCL line low again (i.e., the Counter Register must be set to 14 before
releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If
the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)
The slave can hold the SCL line low after the acknowledge (E).
by the Master (F). Or a new start condition is given.
SDA
SCL
Write( USISIF)
A B
S
C
ADDRESS
SDA
SCL
1 - 7
(Figure 21-6 on page
(Figure 21-5 on page
R/W
8
D
ACK
9
E
DATA
1 - 8
D Q
204) detects the start condition and
204), a bus transfer involves the following
CLR
ACK
9
D Q
CLR
DATA
1 - 8
USISIF
CLOCK
HOLD
ACK
9
P
F
204
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