ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 140
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1
18.2
18.2.1
8285D–AVR–06/11
Features
Overview
Registers
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
•
•
•
•
•
•
•
A simplified block diagram of the 8-bit Timer/Counter is shown in
placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
Figure 18-1. 8-bit Timer/Counter Block Diagram
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter-
rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register
(TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2).
TIFR2 and TIMSK2 are not shown in the figure.
Single Compare Unit Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)
Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock
Status flags
Timer/Counter
”Register Description” on page
TCNTn
OCRnx
=
ASSRn
direction
”Pin Configurations” on page
count
clear
BOTTOM
Synchronized Status flags
= 0
Control Logic
=
TCCRnx
TOP
asynchronous mode
0xFF
select (ASn)
154.
clk
Tn
Synchronization Unit
OCnx
(Int.Req.)
Generation
Prescaler
Waveform
2. CPU accessible I/O Registers,
Figure
Oscillator
T/C
18-1. For the actual
OCnx
clk
TOVn
(Int.Req.)
clk
clk
ASY
I/O
I/O
TOSC1
TOSC2
140
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