ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 130
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ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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16.11 Register Description
16.11.1
8285D–AVR–06/11
TCCR1A – Timer/Counter1 Control Register A
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
• Bit 7:6 – COM1A[1:0]: Compare Output Mode for Unit A
• Bit 5:4 – COM1B[1:0]: Compare Output Mode for Unit B
The COM1A[1:0] and COM1B[1:0] control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A[1:0] bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B[1:0] bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x[1:0] bits is depen-
dent of the WGM1[3:0] bits setting...
WGM1[3:0] bits are set to a Normal or a CTC mode (non-PWM).
Table 16-2.
Table 16-3
PWM mode.
Table 16-3.
Note:
Bit
(0x80)
Read/Write
Initial Value
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at TOP.
Mode” on page 122.
shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the fast
COM1A1
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
COM1A0/COM1B0
R/W
6
0
for more details.
0
1
0
1
0
1
0
1
COM1B1
R/W
5
0
Table 16-2
COM1B0
R/W
4
0
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
Normal port operation, OC1A/OC1B disconnected.
WGM1[3:0] = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BOTTOM (non-inverting mode)
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BOTTOM (inverting mode)
Description
Description
shows the COM1x[1:0] bit functionality when the
(1)
R
3
–
0
R
2
–
0
WGM11
R/W
1
0
WGM10
See ”Fast PWM
R/W
0
0
TCCR1A
130
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