M42800A Atmel Corporation, M42800A Datasheet - Page 125

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

17.4
17.4.1
17.5
1779D–ATARM–14-Apr-06
Transmitter
Multi-drop Mode
Time-guard
Calculation of time-out duration:
The transmitter has the same behavior in both synchronous and asynchronous operating
modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first,
on the falling edge of the serial clock. See example in Figure 17-6.
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR (Transmit Holding), it is transferred to the Shift Regis-
ter as soon as it is empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a
new character is written to US_THR. If Transmit Shift Register and US_THR are both empty,
the TXEMPTY bit in US_CSR is set.
The Time-guard function allows the transmitter to insert an idle state on the TXD line between
two characters. The duration of the idle state is programmed in US_TTGR (Transmitter Time-
guard). When this register is set to zero, no time-guard is generated. Otherwise, the transmit-
ter holds a high level on TXD after each transmitted byte during the number of bit periods
programmed in US_TTGR.
Figure 17-6. Synchronous and Asynchronous Modes: Character Transmission
When the field PAR in US_MR equals 11X (binary value), the USART is configured to run in
Multi-drop mode. In this case, the parity error bit PARE in US_CSR is set when data is
detected with a parity bit set to identify an address byte. PARE is cleared with the Reset Sta-
tus Bits Command (RSTSTA) in US_CR. If the parity bit is detected low, identifying a data
byte, PARE is not set.
The transmitter sends an address byte (parity bit set) when a Send Address Command
(SENDA) is written to US_CR. In this case, the next byte written to US_THR will be transmit-
ted as an address. After this any byte transmitted will have the parity bit cleared.
Duration = Value x 4 x Bit Period
Baud Rate
Example: 8-bit, parity enabled 1 stop
Clock
TXD
Start
Bit
between two characters
D0
Idle state duration
D1
D2
D3
= Time-guard
Value
D4
D5
x
Period
Bit
D6
AT91M42800A
D7
Parity
Bit
Stop
Bit
125