M42800A Atmel Corporation, M42800A Datasheet - Page 84

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

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Interrupt Clearing and Setting
Fast Interrupt Request
Software Interrupt
Spurious Interrupt
AT91M42800A
All interrupt sources which are programmed to be edge triggered (including FIQ) can be indi-
vidually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This
function of the interrupt controller is available for auto-test or software debug purposes.
The external FIQ line is the only source which can raise a fast interrupt request to the proces-
sor. Therefore, it has no priority controller.
The external FIQ line can be programmed to be positive or negative edge triggered or high- or
low-level sensitive in the AIC_SMR0 register.
The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written
into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised.
By storing the following instruction at address 0x0000001C, the processor will load the pro-
gram counter with the interrupt handler address stored in the AIC_FVR register.
Alternatively the interrupt handler can be stored starting from address 0x0000001C as
described in the ARM7TDMI datasheet.
Interrupt source 1 of the advanced interrupt controller is a software interrupt. It must be pro-
grammed to be edge triggered in order to set or clear it by writing to the AIC_ISCR and
AIC_ICCR.
This is totally independent of the SWI instruction of the ARM7TDMI processor.
When the AIC asserts the NIRQ line, the ARM7TDMI enters IRQ mode and the interrupt han-
dler reads the IVR. It may happen that the AIC de-asserts the NIRQ line after the core has
taken into account the NIRQ assertion and before the read of the IVR.
This behavior is called a Spurious Interrupt.
The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the
IVR is read. The Spurious Vector can be programmed by the user when the vector table is
initialized.
A spurious interrupt may occur in the following cases:
The same mechanism of spurious interrupt occurs if the ARM7TDMI reads the IVR (applica-
tion software or ICE) when there is no interrupt pending. This mechanism is also valid for the
FIQ interrupts.
Once the AIC enters the spurious interrupt management, it asserts neither the NIRQ nor the
NFIQ lines to the ARM7TDMI as long as the spurious interrupt is not acknowledged. There-
fore, it is mandatory for the Spurious Interrupt Service Routine to acknowledge the “spurious”
• With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is
• If an interrupt is asserted at the same time as the software is disabling the corresponding
de-asserted at the same time as it is taken into account by the ARM7TDMI.
source through AIC_IDCR (this can happen due to the pipelining of the ARM core).
ldr PC,[PC,# -&F20]
1779D–ATARM–14-Apr-06