M42800A Atmel Corporation, M42800A Datasheet - Page 59

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.4
12.5
1779D–ATARM–14-Apr-06
ARM Processor Clock Controller
Peripheral Clock Controller
save power consumption by setting the bit MCKODS (Master Clock Output Disable) in
PMC_CGMR. After a reset the MCKO pin is enabled and is driven by the Slow Clock.
Figure 12-6. Master Clock Output
The AT91M42800A has only one System Clock. It can be enabled and disabled by writing the
System Clock Enable (PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The
status of this clock (at least for debug purpose) can be read in the System Clock Status Regis-
ter (PMC_SCSR).
The system clock is enabled after a reset and is automatically re-enabled by any enabled
interrupt.
When the system clock is disabled, the current instruction is finished before the clock is
stopped.
Note:
Figure 12-7. System Clock Control
The clock of each peripheral integrated in the AT91M42800A can be individually enabled and
disabled by writing into the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Dis-
able (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the
Peripheral Clock Status Register (PMC_PCSR).
Master Clock
Stopping the ARM core does not prevent PDC transfers.
Slow Clock
SLCK
MCK
NIRQ
NFIQ
PMC_SCDR
Register
Divide by 2
Mode
Idle
Set
Clear
MCKOSS
PMC_SCSR
MCK
Master Clock
MCKODS
AT91M42800A
System
Clock
MCKO
Master Clock Output
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