M42800A Atmel Corporation, M42800A Datasheet - Page 127

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

17.6.2
17.7
17.8
17.9
1779D–ATARM–14-Apr-06
Peripheral Data Controller
Interrupt Generation
Channel Modes
Receive Break
Each of these steps can be scheduled by using the interrupt if the bit TXRDY in US_IMR is
set.
For character transmission, the USART channel must be enabled before sending a break.
The receiver detects a break condition when all data, parity and stop bits are low. When the
low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. An end of receive
break is detected by a high level for at least 2/16 of a bit period in asynchronous operating
mode or at least one sample in synchronous operating mode. RXBRK is also asserted when
an end of break is detected.
Both the beginning and the end of a break can be detected by interrupt if the bit
US_IMR.RXBRK is set.
Each USART channel is closely connected to a corresponding Peripheral Data Controller
channel. One is dedicated to the receiver. The other is dedicated to the transmitter.
The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR.
The PDC channel is programmed using US_TPR (Transmit Pointer) and US_TCR (Transmit
Counter) for the transmitter and US_RPR (Receive Pointer) and US_RCR (Receive Counter)
for the receiver. The status of the PDC is given in US_CSR by the ENDTX bit for the transmit-
ter and by the ENDRX bit for the receiver.
The pointer registers (US_TPR and US_RPR) are used to store the address of the transmit or
receive buffers. The counter registers (US_TCR and US_RCR) are used to store the size of
these buffers.
The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is
triggered by TXRDY. When a transfer is performed, the counter is decremented and the
pointer is incremented. When the counter reaches 0, the status bit is set (ENDRX for the
receiver, ENDTX for the transmitter in US_CSR) and can be programmed to generate an inter-
rupt. Transfers are then disabled until a new non-zero counter value is programmed.
Each status bit in US_CSR has a corresponding bit in US_IER (Interrupt Enable) and US_IDR
(Interrupt Disable) which controls the generation of interrupts by asserting the USART inter-
rupt line connected to the Advanced Interrupt Controller. US_IMR (Interrupt Mask Register)
indicates the status of the corresponding bits.
When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is asserted.
The USART can be programmed to operate in three different test modes, using the field
CHMODE in US_MR.
5. Wait for the transmitter ready
6. Send the next byte
(bit TXRDY = 1 in US_CSR)
(write byte to US_THR)
AT91M42800A
127