M42800A Atmel Corporation, M42800A Datasheet - Page 56
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M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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12.2
Figure 12-4. Master Clock
12.2.1
56
Master Clock
AT91M42800A
Phase Locked Loops
Slow Clock
PLLRCA
PLLRCB
SLCK
Figure 12-2. Slow Clock
To operate correctly, the crystal must be as close to the XIN and XOUT pins as possible. An
external variable capacitor can be added to adjust the oscillator frequency.
Figure 12-3. Crystal Location
The Master Clock (MCK) is generated from the Slow Clock by means of one of the two inte-
grated PLLs and the prescaler.
Note:
Two PLLs are integrated in the AT91M42800A in order to cover a larger frequency range.
Both PLLs have a Slow Clock input and a dedicated pin (PLLRCA or PLLRCB), which must
have appropriate capacitors and resistors. The capacitors and resistors serve as a second
1. Value written at reset and not subsequently programmable.
PLLA
PLLB
MUL
MUL
GROUND
PLANE
XOUT
XIN
PLLS
C
(1)
Source
Clock
PLLCOUNT
Oscillator
32 kHz
PLL Lock Timer
CSS
SLCK
Slow Clock
Prescaler
PRES
GND
XIN
XOUT
Lock
MCK
Master Clock
1779D–ATARM–14-Apr-06
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