M42800A Atmel Corporation, M42800A Datasheet - Page 31

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.9.3
11.10 Write Data Hold Time
1779D–ATARM–14-Apr-06
Early Read Wait State
Figure 11-10. Early Read Protocol
In early read protocol, an early read wait state is automatically inserted when an external write
cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent
read cycle begins (see
grammed wait states (i.e., data float wait).
No wait state is added when a read cycle is followed by a write cycle, between consecutive
accesses of the same type or between external and internal memory accesses.
Early read wait states affect the external bus only. They do not affect internal bus timing.
Figure 11-11. Early Read Wait State
During write cycles in both protocols, output data becomes valid after the falling edge of the
NWE signal and remains valid after the rising edge of NWE, as illustrated in
external NWE waveform (on the NWE pin) is used to control the output data timing to guaran-
tee this operation.
ADDR
MCKI
NWE
NCS
NRD
or
Figure
ADDR
MCKI
NWE
NCS
NRD
Write Cycle
11-11). This wait state is generated in addition to any other pro-
Early Read Wait
Read Cycle
AT91M42800A
Figure
11-12. The
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