M42800A Atmel Corporation, M42800A Datasheet - Page 72

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

13.3
72
RTT: Real-time Timer
AT91M42800A
If an overflow does occur, the Watchdog Timer:
Writing the ST_WDMR does not reload or restart the down counter. When the ST_CR is writ-
ten the watchdog is immediately reloaded from ST_WDMR and restarted. The slow clock 128
divider is also immediately reset and restarted. When the ARM7TDMI enters debug mode, the
output of the slow clock divider stops, preventing any internal or external reset during the
debugging phase.
Figure 13-3. Watchdog Timer
The Real-time Timer can be used to count elapsed seconds. It is built around a 20-bit counter
fed by the Slow Clock divided by a programmable value. At reset this value is set to 0x8000,
corresponding to feeding the real-time counter with a 1 Hz signal when the Slow Clock is
32.768 Hz. The 20-bit counter can count up to 1048576 seconds, corresponding to more than
12 days, then roll over to 0.
The Real-time Timer value can be read at any time in the register ST_CRTR (Current Real-
time Register). As this value can be updated asynchronously to the Master Clock, it is advis-
able to read this register twice at the same value to improve accuracy of the returned value.
This current value of the counter is compared with the value written in the Alarm Register
ST_RTAR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in
ST_SR is set. The Alarm Register is set to its maximum value, corresponding to 0, after a
reset.
The bit RTTINC in ST_SR is set each time the 20-bit counter is incremented. This bit can be
used to start an interrupt, or generate a one-second signal.
Writing the ST_RTMR immediately reloads and restarts the clock divider with the new pro-
grammed value. This also resets the 20-bit counter.
• Sets the WDOVF in ST_SR (Status Register) from which an interrupt can be generated
• Generates a pulse for 8 slow clock cycles on the external signal NWDOVF if the bit EXTEN
• Generates an internal reset if the parameter RSTEN in ST_WDMR is set
• Reloads and restarts the down counter
in ST_WDMR is set
Slow Clock
SLCK
1/128
Watchdog Restart
WDRST
16-bit Down
Counter
WV
Watchdog Value
RSTEN - Reset Enable
EXTEN- External Signal Enable
WDOVF
Watchdog Overflow
Internal Reset
NWDOVF
1779D–ATARM–14-Apr-06