M42800A Atmel Corporation, M42800A Datasheet - Page 30

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.9.1
11.9.2
30
AT91M42800A
Standard Read Protocol
Early Read Protocol
The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is valid
for all memory devices. Standard read protocol is the default protocol after reset.
Note:
Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are
active during the second half of the clock cycle. The first half of the clock cycle allows time to
ensure completion of the previous access as well as the output of address and NCS before the
read cycle begins.
During a standard read protocol, external memory access, NCS is set low and ADDR is valid
at the beginning of the access while NRD goes low only in the second half of the master clock
cycle to avoid bus conflict (see
Figure 11-9. Standard Read Protocol
NWE is the same in both protocols. NWE always goes low in the second half of the master
clock cycle (see
Early read protocol provides more time for a read access from the memory by asserting NRD
at the beginning of the clock cycle. In the case of successive read cycles in the same memory,
NRD remains active continuously. Since a read cycle normally limits the speed of operation of
the external memory system, early read protocol can allow a faster clock frequency to be
used. However, an extra wait state is required in some cases to avoid contentions on the
external bus.
In the following waveforms and descriptions, NRD represents NRD and NOE since the two sig-
nals have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless
NWR0 and NWR1 are otherwise represented. ADDR represents A0 - A23 and/or
A1 - A23.
Figure 11-11 on page
or
ADDR
MCKI
NWE
NRD
NCS
Figure
11-9).
31).
1779D–ATARM–14-Apr-06