M42800A Atmel Corporation, M42800A Datasheet - Page 58

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.2.4
12.2.5
12.2.6
12.3
58
Master Clock Output Controller
AT91M42800A
PLL Programming
PLL Lock Timer
Prescaler
When switching from PLL Output to Slow Clock, the switch takes effect after 3.5 Slow Clock
cycles plus 2.5 PLL output signal cycles. This is a maximum value.
Once the PLL is selected, the output of the active PLL is a multiple of the Slow Clock, deter-
mined by the MUL field of the PMC_CGMR. The value of the multiply factor can be up to 2048.
The multiplication factor is the programmed value plus one (MUL+1).
Each time PMC_CGMR is written with a MUL value different from the existing one, the LOCK
bit in PMC_SR is automatically cleared and the PLL Lock Timer is started (see
”PLL Lock Timer” on page
If a null value is programmed in the MUL field, the PLL is automatically disabled and bypassed
to save power. The LOCK bit in PMC_SR is also automatically cleared.
The time during which the LOCK bit is cleared is user programmable in the field PLLCOUNT in
PMC_CGMR. The user must load this parameter with a value depending on the active PLL
and its start-up time or the frequency shift performed.
As long as the LOCK bit is 0, the PLL is automatically bypassed and its output is the Slow
Clock. This means:
The Power Management Controller of the AT91M42800A integrates a dedicated 8-bit timer for
the locking time of the PLL. This timer is loaded with the value written in PLLCOUNT each
time the value in the field MUL changes. At the same time, the LOCK bit in PMC_SR is
cleared, and the PLL is bypassed.
The timer counts down the value written in PLLCOUNT on the Slow Clock. The countdown
value ranges from 30 µs to 7.8 ms.
When the PLL Lock Timer reaches 0, the LOCK bit is set and can provide an interrupt.
The PLLCOUNT field is defined by the user, and depends on the current state of the PLL
(unlocked or locked), the targeted output frequency and the filter implemented on the PLLRC
pin.
The Clock Source (Slow Clock or PLL output) selected through the CSS field (Clock Source
Select) in PMC_CGMR can be divided by 1, 2, 4, 8, 16, 32 or 64. The default divider after a
reset is 1. The output of the prescaler is called Master Clock (MCK).
When the prescaler value is modified, the new defined Master Clock is effective after a maxi-
mum delay of 64 Source Clock cycles.
The clock output on MCKO pin can be selected to be the Slow Clock, the Master Clock, the
Master Clock inverted or the Master Clock divided by two through the MCKOSS field (Master
Clock Output Source Select) in PMC_CGMR. The MCKO pad can be put in Tri-state mode to
• A switch from the PLL output to the Slow Clock and the associated delays, when the PLL is
• A switch from the Slow Clock to the PLL output and the associated delays, when the LOCK
locked.
bit is set.
58). The LOCK bit is set when the PLL Lock Timer reaches 0.
1779D–ATARM–14-Apr-06
Section 12.2.5