M42800A Atmel Corporation, M42800A Datasheet - Page 33

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M42800A

Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of M42800A

Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
11.11.2
1779D–ATARM–14-Apr-06
Data Float Wait State
Figure 11-13. One Wait State Access
Notes:
Some memory devices are slow to release the external bus. For such devices, it is necessary
to add wait states (data float waits) after a read access before starting a write access or a read
access to a different external memory.
The data float output time (t
field of the EBI_CSR register for the corresponding chip select. The value (0 - 7 clock cycles)
indicates the number of data float waits to be inserted and represents the time allowed for the
data output to go high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long t
memory.
The EBI keeps track of the programmed external data float time during internal accesses, to
ensure that the external memory system is not accessed while it is still busy.
Internal memory accesses and consecutive accesses to the same external memory do not
have added data float wait states.
1. Early Read Protocol
2. Standard Read Protocol
ADDR
MCKI
NWE
NRD
NCS
DF
DF
(1)
) for each external memory device is programmed in the TDF
will not slow down the execution of a program from internal
1 Wait State Access
(2)
AT91M42800A
33

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