M42800A Atmel Corporation, M42800A Datasheet - Page 15

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.7.3
7.7.4
7.7.5
1779D–ATARM–14-Apr-06
Boot Mode Select
Remap Command
Abort Control
bank can be used for stack allocation (to speed up context saving and restoring), or as data
and program storage for critical algorithms.
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
non-volatile memory after the reset.
The input level on the BMS pin during the last 10 SLCK clock cycles before the rising edge of
the NRST selects the type of boot memory. The Boot mode depends on BMS (see
The pin BMS is multiplexed with the I/O line PA27 that can be programmed after reset like any
standard PIO line.
Table 7-2.
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors
to be redefined dynamically by the software, the AT91M42800A microcontroller uses a remap
command that enables switching between the boot memory and the internal SRAM bank
addresses. The remap command is accessible through the EBI User Interface, by writing one
in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if
access to the other external devices (connected to chip selects 1 to 7) is required. The remap
operation can only be changed back by an internal reset or an NRST assertion.
Notes:
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted in the following cases:
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
When the processor performs a forbidden write access in a mode-protected peripheral regis-
ter, the write is cancelled but no abort is generated.
The processor can perform word or half-word data access with a misaligned address when a
register relative load/store instruction is executed and the register contains a misaligned
address. In this case, whether the access is in write or in read, an abort is generated but the
access is not cancelled.
The Abort Status Register traces the source that caused the last abort. The address and the
type of abort are stored in registers of the External Bus Interface.
• When accessing an undefined address in the EBI address space
• When the ARM7TDMI performs a misaligned access
BMS
1. NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level
1
0
sensitive.
Boot Mode Select
Boot Memory
External 8-bit memory NCS0
External 16-bit memory on NCS0
AT91M42800A
Table
7-2).
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