M42800A Atmel Corporation, M42800A Datasheet - Page 83

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

14.2
14.3
14.4
1779D–ATARM–14-Apr-06
Priority Controller
Interrupt Handling
Interrupt Masking
loads the program counter with the interrupt handler address stored in the AIC_IVR register.
Execution is then vectored to the interrupt handler corresponding to the current interrupt.
The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register
(AIC_IVR) is read. The value read in the AIC_IVR corresponds to the address stored in the
Source Vector Register (AIC_SVR) of the current interrupt. Each interrupt source has its cor-
responding AIC_SVR. In order to take advantage of the hardware interrupt vectoring it is
necessary to store the address of each interrupt handler in the corresponding AIC_SVR, at
system initialization.
The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable
priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt at a time, the interrupt with the
highest priority is serviced first. If both interrupts have equal priority, the interrupt with the low-
est interrupt source number (see
The current priority level is defined as the priority level of the current interrupt at the time the
register AIC_IVR is read (the interrupt which will be serviced).
In the case when a higher priority unmasked interrupt occurs while an interrupt already exists,
there are two possible outcomes depending on whether the AIC_IVR has been read.
When the end of interrupt command register (AIC_EOICR) is written, the current interrupt level
is updated with the last stored interrupt level from the stack (if any). Hence at the end of a
higher priority interrupt, the AIC returns to the previous state corresponding to the preceding
lower priority interrupt which had been interrupted.
The interrupt handler must read the AIC_IVR as soon as possible. This de-asserts the NIRQ
request to the processor and clears the interrupt in case it is programmed to be edge trig-
gered. This permits the AIC to assert the NIRQ line again when a higher priority unmasked
interrupt occurs.
At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR)
must be written. This allows pending interrupts to be serviced.
Each interrupt source, including FIQ, can be enabled or disabled using the command registers
AIC_IECR and AIC_IDCR. The interrupt mask can be read in the Read-only register AIC_IMR.
A disabled interrupt does not affect the servicing of other interrupts.
• If the NIRQ line has been asserted but the AIC_IVR has not been read, then the processor
• If the processor has already read the AIC_IVR then the NIRQ line is reasserted. When the
will read the new higher priority interrupt handler address in the AIC_IVR register and the
current interrupt level is updated.
processor has authorized nested interrupts to occur and reads the AIC_IVR again, it reads
the new, higher priority interrupt handler address. At the same time the current priority
value is pushed onto a first-in last-out stack and the current priority is updated to the higher
priority.
ldr PC,[PC,# -&F20]
Table
14-1) is serviced first.
AT91M42800A
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