SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 124

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

17.4.6
Register Name: SUPC_WUMR
Access Type: Read-write
• FWUPEN: Force Wake Up Enable
0 = The Force Wake Up pin has no wake up effect.
1 = The Force Wake Up pin low forces the wake up of the core power supply.
• BODEN: Brownout Wake Up Enable
0 = The brownout alarm signal has no wake up effect.
1 = The brownout alarm signal forces the wake up of the core power supply.
• RTCEN: Real Time Clock Wake Up Enable
0 = The RTC alarm signal has no wake up effect.
1 = The RTC alarm signal forces the wake up of the core power supply.
• FWUPDBC: Force Wake Up Debouncer
• WUPDBC: Wake Up Inputs Debouncer
124
31
23
15
–
–
–
7
–
FWUPDBC
WUPDBC
AT91SAM7L128/64 Preliminary
Supply Controller Wake Up Mode Register
0x6-0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x0
0x1
0x2
30
22
14
–
–
6
–
Force Wake Up Debouncer
Immediate, no debouncing, detected active at least on one Slow Clock edge.
FWUP shall be low for at least 3 SLCK periods
FWUP shall be low for at least 32 SLCK periods
FWUP shall be low for at least 512 SLCK periods
FWUP shall be low for at least 4,096 SLCK periods
FWUP shall be low for at least 32,768 SLCK periods
Reserved
Immediate, no debouncing, detected active at least on one Slow Clock edge.
An enabled wake-up input shall be active for at least 3 SLCK periods
An enabled wake-up input shall be active for at least 32 SLCK periods
Wake Up Inputs Debouncer
WKUPDBC
29
21
13
–
–
5
–
28
20
12
–
–
4
–
RTCEN
27
19
11
–
–
–
3
26
18
10
–
–
2
–
FWUPDBC
BODEN
25
17
–
–
9
1
6257A–ATARM–20-Feb-08
FWUPEN
24
16
–
–
8
0