SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 162

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 20-5.
20.2.5
20.2.5.1
20.2.5.2
162
Step
9
10
11
12
13
AT91SAM7L128/64 Preliminary
Device Operations
Programmer Action
Sets NOE signal
Waits for NVALID high
Sets DATA in output mode
Sets NCMD signal
Waits for RDY high
Flash Read Command
Flash Write Command
Read Handshake (Continued)
Several commands on the Flash memory are available. These commands are summarized in
Table 20-3 on page
face running several read/write handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining
a read command after a write automatically flushes the load buffer in the Flash.
This command is used to read the contents of the Flash memory. The read command can start
at any valid address in the memory plane and is optimized for consecutive reads. Read hand-
shaking can be chained; an internal address buffer is automatically increased.
Table 20-6.
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load
buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the
Flash:
Step
1
2
3
4
5
...
n
n+1
n+2
n+3
...
• before access to any page other than the current one
• when a new command is validated (MODE = CMDE)
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Read Command
159. Each command is driven by the programmer through the parallel inter-
Sets NVALID signal
Waits for NCMD high
Sets RDY signal
Device Action
Sets DATA bus in input mode
MODE[3:0]
CMDE
ADDR0
ADDR1
DATA
DATA
...
ADDR0
ADDR1
DATA
DATA
...
DATA[15:0]
READ
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
DATA I/O
Output
X
Input
Input
Input
6257A–ATARM–20-Feb-08