SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 43
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SAM7L128
Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L128
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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10.12 Analog-to-Digital Converter
10.13 Segment LCD Controller
6257A–ATARM–20-Feb-08
The Segment LCD Controller/driver is intended for monochrome passive liquid crystal display
(LCD) with up to 10 common terminals and up to 40 segment terminals.
• Independent channel programming
• 4-channel ADC supplied by the internal voltage regulator
• 10-bit 460 Ksamples/sec. or 8-bit 660 Ksamples/sec. Successive Approximation Register
• ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity
• Integrated 4-to-1 multiplexer
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger sources
• Sleep Mode and conversion sequencer
• 40 segments and 10 common terminals display capacity
• Support static, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 Duty
• Support static, 1/2, 1/3, 1/4 Bias
• Power-save mode display
• Software-selectable low-power waveform capability
• Flexible frame frequency selection
• Segment and common pins, not needed for driving the display, can be used as ordinary I/O
• Switching time enhancement internal buffers
ADC
pins
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
AT91SAM7L128/64 Preliminary
43
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