SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 217

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

24.6.2
6257A–ATARM–20-Feb-08
Divider and Phase Lock Loop Programming
Figure 24-5. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade off has to be
found between output signal overshoot and startup time. See the product electrical PLL charac-
teristics section.
Note that PLLRCGND must never be connected to GND.
The divider can only be set at 1 when the PLL is activated. The PLL input is SLCK.
When the divider field (DIV) is set to 0, the output of the corresponding divider and the PLL out-
put is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding
PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that
depends on the respective source signal frequency and on the MUL parameter. The factor
applied to the source signal frequency is (MUL + 1). When MUL is written to 0, the correspond-
ing PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed
by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR
is automatically cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded
in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it
reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the pro-
cessor. The user has to load the number of Slow Clock cycles required to cover the PLL
transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial
state of the PLL and its target frequency can be calculated using a specific tool provided by
Atmel.
Two PLL startup schemes are available:
Note that the STMODE field of the CKGR_PLLR register must be set to 0x02 when the PLL is
shutdown.
• The fast startup scheme allows the PLL to reach at least 70% of its target frequency in less
• The normal startup procedure of the PLL is performed when the STDMODE field of the
than 60 µs. In this mode the STDMODE field must be set to 0x0 and the PLLCOUNT field
can be programed at 0x01 in the CKGR_PLLR register.
CKGR_PLLR register is set to 0x02. In this startup scheme, the PLLCOUNT field must be set
with the relevant value function of the programed PLL frequency.
C2
AT91SAM7L128/64 Preliminary
R
C1
PLLRC
PLLRCGND
PLL
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