SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 220

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.6
25.7
220
The Fast Startup
Programming Sequence
AT91SAM7L128/64 Preliminary
The SAM7L device allows the processor to restart in less than six microseconds while the device
is in Wait mode. A Fast Startup is enabled upon the detection of a low level on one of the 16
wake-up inputs.
The Fast Restart circuitry, as shown in
startup signal to the Power Management Controller. As soon as the fast startup signal is
asserted, this automatically restarts the embedded 2 MHz Fast RC oscillator, switches the Mas-
ter Clock on the 2 MHz clock and re-enables the processor clock if it is disabled.
Figure 25-2. Fast Startup Circuitry
Each wake-up input pin can be enabled to generate a Fast Startup event by writing at 1 the cor-
responding bit in the Fast Startup Mode Register SUPC_FSMR. Only a low level on the enabled
wake-up input pins generates a Fast Startup.
The user interface does not provide any status for Fast Startup, but the user can easily recover
this information by reading the PIO Controller.
7. Checking the Main Oscillator Frequency (Optional):
8. Setting PLL and divider:
In some situations the user may need an accurate measure of the main clock frequency.
This measure can be accomplished via the CKGR_MCFR register.
Once the MAINFRDY field is set in CKGR_MCFR register, the user may read the MAINF
field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen
slow clock cycles.
All parameters needed to configure PLL and the divider are located in the CKGR_PLLR
register.
The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By
default, DIV parameter is set to 0 which means that the divider is turned off.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0
and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is
PLL input frequency multiplied by (MUL + 1).
WKUP15
WKUP0
WKUP1
FSTT15
FSTT0
FSTT1
Figure
25-2, is fully asynchronous and provides a fast
fast_restart
6257A–ATARM–20-Feb-08