SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 145

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.3.2.2
Figure 19-5. Data Read Optimization in ARM Mode for FWS = 1
19.3.3
6257A–ATARM–20-Feb-08
Buffer (128bits)
Flash Access
ARM Request
Data To ARM
Master Clock
(32-bit)
Flash Commands
Data Read Optimization
@Byte 0
XXX
XXX
XXX
The organization of the Flash in 128 bits is associated with two 128-bit prefetch buffers and one
128-bit data read buffer, thus providing maximum system performance. This buffer is added in
order to start access at the following data during the second read. This speeds up sequential
data reads if, for example, FWS is equal to 1 (see
Note:
The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as program-
ming the memory Flash, locking and unlocking lock regions, consecutive programming and
locking and full Flash erasing, etc.
Commands and read operations can be performed in parallel only on different memory planes.
Code can be fetched from one memory plane while a write or an erase operation is performed
on another.
Table 19-1.
Bytes 0-15
Command
Get Flash Descriptor
Write page
Write page and lock
Erase page and write page
Erase page and write page then lock
Erase all
Set Lock Bit
Clear Lock Bit
Get Lock Bit
Bytes 0-3
@ 4
No consecutive data read accesses are mandatory to benefit from this optimization.
Set of Commands
@ 8
4-7
@ 12
8-11
Bytes 0-15
12-15
@ 16
AT91SAM7L128/64 Preliminary
Bytes 16-31
@ 20
16-19
Figure
@ 24
20-23
19-5).
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x8
0x9
0xA
24-27
@ 28
Bytes 16-31
28-31
@ 32
Mnemonic
GETD
WP
WPL
EWP
EWPL
EA
SLB
CLB
GLB
Bytes 32-47
@ 36
32-35
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