SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 168

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SAM7L128

Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7L128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
20.3.3
168
AT91SAM7L128/64 Preliminary
Read/Write Handshake
Table 20-17. Reset TAP Controller and Go to Select-DR-Scan
The read/write handshake is done by carrying out read/write operations on two registers of the
device that are accessible through the JTAG:
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data
field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit
data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A
register is read by scanning its address into the address field and 0 into the read/write bit, going
through the UPDATE-DR TAP state, then scanning out the data.
Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.
Figure 20-7. TAP 8-bit DR Register
A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE
1149.1 for more details on JTAG operations.
• Debug Comms Control Register: DCCR
• Debug Comms Data Register: DCDR
• The address of the Debug Comms Control Register is 0x04.
• The address of the Debug Comms Data Register is 0x05.
TDI
The Debug Comms Control Register is read-only and allows synchronized handshaking
between the processor and the debugger.
– Bit 1 (W): Denotes whether the programmer can read a data through the Debug
Comms Data Register. If the device is busy W = 0, then the programmer must poll
until W = 1.
r/w
TDI
Xt
X
X
X
X
X
X
4
Address
Address
Decoder
5
0
31
TMS
1
1
1
1
1
0
1
TAP Controller State
Test-Logic Reset
Run-Test/Idle
Select-DR-Scan
Debug Comms Control Register
Debug Comms Data Register
Data
32
6257A–ATARM–20-Feb-08
0
TDO

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