SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 150

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.3.3.5
150
AT91SAM7L128/64 Preliminary
GPNVM Bit
One error can be detected in the MC_FSR register after a programming sequence:
It is possible to clear lock bits previously set. Then the locked region can be erased or pro-
grammed. The unlock sequence is:
One error can be detected in the MC_FSR register after a programming sequence:
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC).
The Get Lock Bit status sequence is:
For example, if the third bit of the first word read in the MC_FRR is set, then the third lock region
is locked.
One error can be detected in the MC_FSR register after a programming sequence:
Note:
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to the product defi-
nition section for information on the GPNVM Bit Action.
The set GPNVM bit sequence is:
• When the locking completes, the bit FRDY in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the MC_FCR register.
• The Clear Lock command (CLB) and a page number to be unprotected are written in the
• When the unlock completes, the bit FRDY in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the MC_FCR register.
• The Get Lock Bit command (GLB) is written in the Flash Command Register. FARG field is
• When the command completes, the bit FRDY in the Flash Programming Status Register
• Lock bits can be read by the software application in the MC_FRR register. The first word read
• a Command Error: a bad keyword has been written in the MC_FCR register.
• Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
effect. The result of the SLB command can be checked running a GLB (Get Lock Bit)
command.
Flash Command Register.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
effect.
meaningless.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is
meaningful. Extra reads to the MC_FRR register return 0.
SGPB command and the number of the GPNVM bit to be set.
Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.
6257A–ATARM–20-Feb-08