SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 453

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SAM7L128

Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7L128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
32. Pulse Width Modulation Controller (PWM)
32.1
32.2
Figure 32-1. Pulse Width Modulation Controller Block Diagram
6257A–ATARM–20-Feb-08
Overview
Block Diagram
PMC
The PWM macrocell controls several channels independently. Each channel controls one
square output waveform. Characteristics of the output waveform such as period, duty-cycle and
polarity are configurable through the user interface. Each channel selects and uses one of the
clocks provided by the clock generator. The clock generator provides several clocks resulting
from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a
double buffering system in order to prevent an unexpected output waveform while modifying the
period or the duty-cycle.
MCK
Clock Generator
Channel
Selector
Channel
Selector
PWMx
PWM0
Clock
Clock
APB Interface
Controller
PWM
Duty Cycle
Duty Cycle
Counter
Counter
Update
Update
APB
Period
Period
AT91SAM7L128/64 Preliminary
Comparator
Comparator
Interrupt Generator
PIO
AIC
PWMx
PWMx
PWM0
PWM0
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