SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 151

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.3.3.6
6257A–ATARM–20-Feb-08
Security Bit Protection
One error can be detected in the MC_FSR register after a programming sequence:
It is possible to clear GPNVM bits previously set. The clear GPNVM bit sequence is:
One error can be detected in the MC_FSR register after a programming sequence:
The status of GPNVM bits can be returned by the Enhanced Embedded Flash Controller
(EEFC). The sequence is:
For example, if the third bit of the first word read in the MC_FRR is set, then the third GPNVM bit
is active.
One error can be detected in the MC_FSR register after a programming sequence:
Note:
When the security is enabled, access to the Flash, either through the ICE interface or through
the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code
programmed in the Flash.
The security bit is GPNVM0.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full
Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are
permitted.
• When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register
• If the GPNVM bit number is greater than the total number of GPNVM bits, then the command
• A Command Error: a bad keyword has been written in the MC_FCR register.
• Start the Clear GPNVM Bit command (CGPB) by writing the Flash Command Register with
• When the clear completes, the bit FRDY in the Flash Programming Status Register
• If the GPNVM bit number is greater than the total number of GPNVM bits, then the command
• A Command Error: a bad keyword has been written in the MC_FCR register.
• Start the Get GPNVM bit command by writing the Flash Command Register with GGPB. The
• When the command completes, the bit FRDY in the Flash Programming Status Register
• GPNVM bits can be read by the software application in the MC_FRR register. The first word
• a Command Error: a bad keyword has been written in the MC_FCR register.
(MC_FSR) rises. If an interrupt was enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
has no effect. The result of the SGPB command can be checked by running a GGPB (Get
GPNVM Bit) command.
CGPB and the number of the GPNVM bit to be cleared.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
has no effect.
FARG field is meaningless.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM
bits as long as it is meaningful. Extra reads to the MC_FRR register return 0.
Access to the Flash in read is permitted when a set, clear or get GPNVM bit command is
performed.
AT91SAM7L128/64 Preliminary
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