SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1013

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 44-2.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Bit
31:0
31
30
Byte Address of buffer
Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer
of a frame once it has been successfully transmitted.
Software has to clear this bit before the buffer can be used again.
Note:
Wrap. Marks last descriptor in transmit buffer descriptor list.
Transmit Buffer Descriptor Entry
This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used.
the control word is read if transmission is to happen. It is written to one when a frame has been
transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit 30 is the “wrap” bit
which can be set for any buffer within a frame. If no wrap bit is encountered after 1024 descrip-
tors, the queue pointer rolls over to the start in a similar fashion to the receive queue.
The transmit buffer queue pointer register must not be written while transmit is active. If a new
value is written to the transmit buffer queue pointer register, the queue pointer resets itself to
point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network
control, the transmit buffer queue pointer register resets to point to the beginning of the transmit
queue. Note that disabling receive does not have the same effect on the receive queue pointer.
Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start
bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set
is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control
register. (Transmission is suspended if a pause frame is received while the pause enable bit is
set in the network configuration register.) Rewriting the start bit while transmission is active is
allowed.
Transmission control is implemented with a Tx_go variable which is readable in the transmit sta-
tus register at bit location 3. The Tx_go variable is reset when:
To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take
effect until any ongoing transmit finishes. If a collision occurs during transmission of a multi-buf-
fer frame, transmission automatically restarts from the first buffer of the frame. If a “used” bit is
read midway through transmission of a multi-buffer frame, this is treated as a transmit error.
Transmission stops, tx_er is asserted and the FCS is bad.
If transmission stops due to a transmit error, the transmit queue pointer resets to point to the
beginning of the transmit queue. Software needs to re-initialize the transmit queue after a trans-
mit error.
If transmission stops due to a “used” bit being read at the start of the frame, the transmission
queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the
transmit start bit is written
– transmit is disabled
– a buffer descriptor with its ownership bit set is read
– a new value is written to the transmit buffer queue pointer register
– bit 10, tx_halt, of the network control register is written
– there is a transmit error such as too many retries or a transmit underrun.
Word 0
Word 1
Function
SAM9G35
SAM9G35
1013
1013