SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1068

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.6.2.5
45.6.2.6
1068
1068
SAM9G35
SAM9G35
DMA Interrupt Generation
DMA Address Alignment Requirements
The DMA controller operation sets the following interrupt flags in the interrupt status register
CHXISR:
When programming the DSCR.CHXADDR field of the DSCR structure the following requirement
must be met.
Table 45-5.
Table 45-6.
1 bpp
2 bpp
4 bpp
8 bpp
12 bpp RGB 444
16 bpp ARGB 4444
16 bpp RGBA 4444
16 bpp RGB 565
16 bpp TRGB 1555
18 bpp RGB 666
18 bpp RGB 666 PACKED
19 bpp TRGB 1666
19 bpp TRGB 1666
24 bpp RGB 888
24 bpp RGB 888 PACKED
25 bpp TRGB 1888
32 bpp ARGB 8888
32 bpp RGBA 8888
• DMA field indicates that the DMA transfer is completed.
• DSCR field indicates that the descriptor structure is loaded in the DMA controller.
• ADD field indicates that a descriptor has been added to the descriptor queue.
• DONE field indicates that the channel transfer has terminated and the channel is
automatically disabled.
CLUT Mode
RGB Mode
DMA address alignment when CLUT Mode is selected
DMA address alignment when RGB Mode is selected
8 bit
8 bit
8 bit
8 bit
16 bit
16 bit
16 bit
16 bit
16 bit
32 bit
8 bit
32 bit
8 bit
32 bit
8 bit
32 bit
32 bit
32 bit
DMA address alignment
DMA address alignment
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11