SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 754

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.7.11
Name:
Address:
Access:
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
754
754
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
31
23
15
7
256, 512, or 1024). The resulting period formula will be:
256, 512, or 1024). The resulting period formula will be:
------------------------------ -
----------------------------------------- -
---------------------------------------- -
--------------------------------------------------- -
X CPRD
CRPD DIVA
2 X CPRD
2 CPRD
SAM9G35
SAM9G35
PWM Channel Period Register
MCK
MCK
MCK
MCK
DIVA
30
22
14
PWM_CPRD[0..3]
0xF8034208 [0], 0xF8034228 [1], 0xF8034248 [2], 0xF8034268 [3]
6
Read-write
or
--------------------------------------------- -
or
CRPD DIVAB
--------------------------------------------------- -
2
MCK
CPRD
29
21
13
MCK
5
DIVB
28
20
12
4
CPRD
CPRD
CPRD
CPRD
27
19
11
3
26
18
10
2
25
17
9
1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
24
16
8
0