SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 63

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• usePmecc: Use PMECC
0 = Do not use PMECC to detect and correct the data.
1 = Use PMECC to detect and correct the data.
• nbSectorPerPage: Number of sectors per page
• spareSize: Size of the spare zone in bytes
• eccBitReq: Number of ECC bits required
• sectorSize: Size of the ECC sector
0 = for 512 bytes.
1 = for 1024 bytes per sector.
Other value for future use.
• eccOffset: Offset of the first ECC byte in the spare zone
A value below 2 is not allowed and will be considered as 2.
• key: value 0xC must be written here to validate the content of the whole word.
If the header is valid, the Boot Program will continue with the detection of valid code.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
NAND Flash Specific Header Detection
31
23
15
7
eccBitReq
30
22
14
6
spareSize
This is the first method used to determine NAND Flash parameters. After Initialization and Reset
command, the Boot Program reads the first page without ECC check, to determine if the NAND
parameter header is present. The header is made of 52 times the same 32-bit word (for redun-
dancy reasons) which must contain NAND and PMECC parameters used to correctly perform
the read of the rest of the data in the NAND. This 32-bit word is described below:
key
29
21
13
5
eccOffset
28
20
12
4
27
19
11
3
-
nbSectorPerPage
spareSize
26
18
10
2
eccOffset
25
17
9
1
sectorSize
SAM9G35
SAM9G35
usePmecc
24
16
8
0
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