SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 427
SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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30.3
Figure 30-1.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
AHB Slave Interface 0
AHB Slave Interface 1
AHB Slave Interface 2
AHB Slave Interface 3
DDRSDRC Module Diagram
DDRSDRC Module Diagram
APB
DDRSDRC is partitioned in two blocks (see
• An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four
• A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
AHB masters and integrates an arbiter.
Stage
Stage
Stage
Stage
Input
Input
Input
Input
Interconnect Matrix
Interface APB
Output
Arbiter
Stage
SDRAM Signal Management
Refresh Management
Asynchronous Timing
DDR-SDR Controller
Finite State Machine
Power Management
Memory Controller
Figure
30-1):
Addr, DQM
ras,cas,we
cke
clk/nclk
DQS
Data
odt
DDR-SDR
SAM9G35
SAM9G35
Devices
427
427
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