SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 473
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SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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31. DMA Controller (DMAC)
31.1
31.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Description
Embedded Characteristics
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMAC embeds 8 channels.
• Two DMACs
• DMAC0 is full featured and optimized for memory-to-memory transfers thanks to the 64-word
• DMAC1 is optimized for peripheral-to-memory transfers, without PIP support
• Acting as Two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
• Channel Buffering
• Channel Control
FIFO on channel 0
– Source/Destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
– Gather support for extracting fields from a system memory area into a contiguous
– User enabled auto-reloading of source, destination and control registers from initially
– Auto-loading of source, destination and control registers from system memory at end
– Unaligned system address to data transfer width supported in hardware
– Picture-In-Picture Mode (on DMAC0 only)
– 16-word FIFO (64-word for channel 0 of DMAC0)
– Automatic packing/unpacking of data to fit FIFO width
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
lists
transfer. Writing a stream of data into non-contiguous fields in system memory
transfer
programmed values at the end of a block transfer
of block transfer in block chaining mode
SAM9G35
SAM9G35
473
473
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