SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 649

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

34.14.8
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• CSTOCYC: Completion Signal Timeout Cycle Number
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block trans-
fers. Its value is calculated by (CSTOCYC x Multiplier).
• CSTOMUL: Completion Signal Timeout Multiplier
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block trans-
fers. Its value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data
transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If
a non-DATA ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the comple-
tion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag
(CSTOE) in the HSMCI Status Register (HSMCI_SR) raises.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
31
23
15
–
–
–
7
–
Value
HSMCI Completion Signal Timeout Register
0
1
2
3
4
5
6
7
30
22
14
HSMCI_CSTOR
0xF000801C (0), 0xF000C01C (1)
Read-write
–
–
–
6
1048576
65536
Name
1024
4096
CSTOMUL
128
256
16
1
29
21
13
–
–
–
5
Description
CSTOCYC x 1
CSTOCYC x 16
CSTOCYC x 128
CSTOCYC x 256
CSTOCYC x 1024
CSTOCYC x 4096
CSTOCYC x 65536
CSTOCYC x 1048576
28
20
12
–
–
–
4
“HSMCI Write Protect Mode Register” on page
27
19
11
–
–
–
3
26
18
10
–
–
–
2
CSTOCYC
25
17
–
–
9
–
1
SAM9G35
SAM9G35
664.
24
16
–
–
8
–
0
649
649