SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 425

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30. DDR SDR SDRAM Controller (DDRSDRC)
30.1
30.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Description
Embedded Characteristics
The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are inter-
leaved to maximize memory bandwidth and minimize transaction latency due to SDRAM
protocol.
The DDRSDRC extends the memory capabilities of a chip by providing the interface to an exter-
nal 16-bit or 32-bit SDR-SDRAM device and external 16-bit DDR-SDRAM device. The page size
supports ranges from 2048 to 16384 and the number of columns from 256 to 4096. It supports
byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The DDRSDRC supports a read or write burst length of 8 locations which frees the command
and address bus to anticipate the next command, thus reducing latency imposed by the SDRAM
protocol and improving the SDRAM bandwidth. Moreover it keeps track of the active row in each
bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank
and data in the other banks. So as to optimize performance, it is advisable to avoid accessing
different rows in the same bank. The DDRSDRC supports a CAS latency of 2 or 3 and optimizes
the read access depending on the frequency.
The features of self refresh, power-down and deep power-down modes minimize the consump-
tion of the SDRAM device.
The DDRSDRC user interface is compliant with ARM Advanced Peripheral Bus (APB rev2).
Note: The term “SDRAM device” regroups SDR-SDRAM, Low-power SDR-SDRAM, Low-
power DDR1-SDRAM and DDR2-SDRAM devices.
• AMBA Compliant Interface, interfaces Directly to the ARM Advanced High performance Bus
• Supports DDR2-SDRAM, Low-power DDR1-SDRAM or DDR2-SDRAM, SDR-SDRAM and
• Numerous Configurations Supported
• Programming Facilities
(AHB)
Low-power SDR-SDRAM
– Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth
– AHB Transfer: Word, Half Word, Byte Access
– 2K, 4K, 8K, 16K Row Address Memory Parts
– SDRAM with Four and Eight Internal Banks
– SDR-SDRAM with 16- or 32-bit Data Path
– DDR-SDRAM with 16-bit Data Path
– One Chip Select for SDRAM Device (256 Mbyte Address Space)
– Multibank Ping-pong Access (Up to or 4 Banks or 8 banks Opened at Same Time =
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
and Minimizes Transaction Latency
Reduces Average Latency of Transactions)
SAM9G35
SAM9G35
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