AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 1051

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

Figure 34-6. PC reset by QEPI signal (TOP.PCTOP = 79, CF.IDXPHS =”00”, CF.IDXE = “1”)
34.6.1.8
34.6.1.9
34.6.2
34.6.2.1
9166C–AVR-08/11
Advanced Operation
Quadrature frequency
Disabling the QDEC
Compare register
IDXERR
QPulse
QEPA
QEPB
QEPI
The CLK_QDEC clock frequency must be at least two times the QEPA and QEPB frequency as
these signals are synchronized to the CLK_QDEC clock. To get the maximum available fre-
quency on QEPA/QEPB signals, the filter on inputs should be bypassed.
For a 33 MHz peripheral bus clock the maximum QEPA frequency is 16.5 MHz. For a wheel with
8192 lines the maximum rotational speed supported by QDEC is 16.5MHz / 8192 = 2014 rps =
120 849 rpm.
The QDEC is disabled by writing a zero to CTRL.CLKEN.
The Compare register (CMP) is used to generate an interrupt and a peripheral event when the
CNT register reaches the value defined in CMP.
If RC compare is enabled (CF.RCCE is one), a compare match occurs when RC is equal to
RCCMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
If the PC compare is enabled (CF.PCCE is one), a compare match occurs when the PC is equal
to PCCMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
If both RC compare and PC compare are enabled, a compare match occurs when CNT is equal
to CMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
The compare peripheral event should be mapped through the PEVC to another peripheral.
RC
PC
72
73
0
74
75
0
1
2
1
3
2
1
0
79
0
78
77
AT32UC3C
1051