AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 880

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

32.6.2.10
9166C–AVR-08/11
RAM management
Endpoint data can be physically allocated anywhere in the embedded RAM. The USBC control-
ler accesses these endpoints directly through the HSB master (built-in DMA).
The USBC controller reads the USBC descriptors to know where each endpoint is located. The
base address of the USBC descriptor (UDESC.UDESCA) needs to be written by the user. The
descriptors can also be allocated anywhere in the embedded RAM.
Before using an endpoint, the user should setup the endpoint address for each bank. Depending
on the direction, the type, and the packet-mode (single or multi-packet), the user should also ini-
tialize the endpoint packet size, and the endpoint control and status fields, so that the USBC
controller does not compute random values from the RAM.
When using an endpoint the user should read the UESTAX.CURRBK field to know which bank
is currently being processed.
• The user may then write a one to the remote wakeup (RMWKUP) bit in UDCON to send an
• When the controller sends the Upstream Resume, the Upstream Resume (UPRSM) interrupt
• RMWKUP is cleared at the end of the transmitting Upstream Resume.
• In case of a rebroadcast resume initiated by the host, the End of Resume (EORSM) interrupt
Upstream Resume to the host initiating the wakeup. This will automatically be done by the
controller after 5ms of inactivity on the USB bus.
is set and SUSP is cleared.
is set when the rebroadcast resume is completed.
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