AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 628
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #2
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
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•
Table 25-19.
•
•
Table 25-20.
•
Table 25-21.
9166C–AVR-08/11
PAR: Parity Type
SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
CHRL: Character Length.
USCLKS: Clock Selection
0
0
0
0
1
1
0
0
1
1
If USART does not operate in SPI Mode (MODE is … 0xE and 0xF):
SYNC = 0: USART operates in Asynchronous Mode.
SYNC = 1: USART operates in Synchronous Mode.
If USART operates in SPI Mode (MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with
0
0
1
1
CPOL to produce the required clock/data relationship between master and slave devices.
USCLKS
CHRL
PAR
0
0
1
1
0
1
0
1
0
1
Note:
0
1
0
1
0
1
0
1
x
x
1. The value of DIV is device dependent. Please refer to the Module Configuration section at the
Character Length
5 bits
6 bits
7 bits
8 bits
end of this chapter.
Parity Type
Even parity
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
Selected Clock
CLK_USART
CLK_USART/DIV
Reserved
CLK
(1)
AT32UC3C
628
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