AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 708

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

Figure 27-13. Combining a Read and Write Transfer
27.8.8
27.8.8.1
Figure 27-14. A Write Transfer with 10-bit Addressing
27.8.8.2
9166C–AVR-08/11
SR.IDLE
RXRDY
TXRDY
TWD
RHR
THR
Ten Bit Addressing
S
Master Transmitter
Master Receiver
SADR
S
1
R
SLAVE ADDRESS
1
To generate this transfer:
Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers
with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of
CMDR.SADR must be written appropriately.
In
white boxes are driven by the slave.
To perform a master transmitter transfer:
When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-
trolled. CMDR.REPSAME must be written to one when the address phase of the transfer should
consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard
specifies that such addressing is required when addressing a slave for reads using 10-bit
addressing.
To perform a master receiver transfer:
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.RXRDY==1, then read first data byte received from RHR.
4. Wait until SR.RXRDY==1, then read second data byte received from RHR.
5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the
1
TWI_RHR
Figure 27-14
1st 7 bits
A
Read
1
desired address and NBYTES value.
0
DATA0
X
X
and
RW A1
0
DATA0
A
Figure
DATA1
SLAVE ADDRESS
27-15, the grey boxes represent signals driven by the master, the
2nd byte
DATA3
A
Sr
DADR
A2
1
DATA
W
A
A
DATA2
DATA2
DATA
A
AA
AT32UC3C
P
DATA3
DATA3
NA
P
708
2