AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 703
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #2
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
- Current page: 703 of 1312
- Download datasheet (20Mb)
Figure 27-7. Master Write with Multiple Data Bytes
27.8.4
9166C–AVR-08/11
SR.IDLE
TXRDY
TWD
Master Receiver Mode
NBYTES set to n
S
Write THR
(DATAn)
DADR
does not acknowledge the data byte. As with the other status bits, an interrupt can be generated
if enabled in the Interrupt Enable Register (IER).
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of a command is marked by writing a one to the SR.CCOMP bit. See
Figure
Figure 27-6. Master Write with One Data Byte
A START condition is transmitted and master receiver mode is initiated when the bus is free and
CMDR has been written with START=1 and READ=1. START and SADR+R will then be trans-
mitted. During the address acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master
polls the data line during this clock pulse and writes a one to the Address Not Acknowledged bit
(ANAK) in the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
SR.IDLE
1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state
2. Release TWCK generating a clock that the slave uses to transmit a data byte.
3. Place the received data byte in RHR, write a one to RXRDY.
4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK.
TXRDY
W
of RHR. Software or the Peripheral DMA Controller must read any data byte present in
RHR.
TWD
27-7.
A
Write THR (DATA)
NBYTES set to 1
S
(DATAn+1)
Write THR
DATAn
DADR
A
W
A
DATAn+5
Last data sent
(DATAn+m)
Write THR
DATA
(ACK received and NBYTES=0)
A
STOP sent automatically
A
DATAn+m
P
(ACK received and NBYTES=0)
STOP sent automatically
A
AT32UC3C
P
Figure 27-6
and
703
Related parts for AT32UC3C2512C Automotive
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet: