AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 898
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #2
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
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- Download datasheet (20Mb)
9166C–AVR-08/11
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI shall be cleared by software to acknowledge the interrupt. This is done by writing a one
to the Transmitted OUT Data Interrupt Clear bit (UPCONnCLR.TXOUTIC), which does not affect
the pipe FIFO.
The user writes the OUT data to the bank referenced to by the PEPn descriptor and allows the
USBC to send the data by writing a one to the FIFO Control Clear (UPCONnCLR.FIFOCONC)
bit. This will also cause a switch to the next bank if the OUT pipe is composed of multiple banks.
The TXOUTI and FIFOCON bits will be updated accordingly
TXOUTI shall always be cleared before clearing FIFOCON to avoid missing an TXOUTI event.
Note that if the user decides to switch to the Suspend state (by writing a zero to UHCON.SOFE)
while a bank is ready to be sent, the USBC automatically exits this state and sends the data.
Figure 32-21. Example of an OUT pipe with one data bank
Figure 32-22. Example of an OUT pipe with two data banks and no bank switching delay
SW
SW
write data to CPU
write data to CPU
BANK 0
BANK 0
SW
OUT
SW
OUT
SW
(bank 0)
DATA
write data to CPU
BANK 1
(bank 0)
DATA
ACK
HW
HW
ACK
SW
OUT
SW
SW
write data to CPU
(bank 1)
DATA
write data to CPU
BANK 0
BANK0
AT32UC3C
ACK
SW
OUT
898
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