ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 107

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
Note:
17.4.6
Figure 50. Clearing the WCOL bit (write collision flag) software sequence
Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
Single master and multimaster configurations
There are two types of SPI systems:
●
●
Single master system
A typical single master system may be configured, using a
device
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave
device during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Multimaster system
A multimaster system may also be configured by the user. Transfer of master control could
be implemented using a handshake method through the I/O ports or by an exchange of
code messages through the serial peripheral interface system.
The multimaster system is principally handled by the MSTR bit in the SPICR register and
the MODF bit in the SPICSR register.
1st Step
2nd Step
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Clearing sequence before SPIF = 1 (during a data byte transfer)
s as slaves (see
Single Master System
Multimaster System
1st Step
2nd Step
Read SPICSR
Read SPIDR
Figure
RESULT
SPIF =0
WCOL=0
Read SPIDR
Read SPICSR
51).
RESULT
WCOL=0
Serial peripheral interface (SPI)
device
as the master and four
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