ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 91

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
16.3
DALI standard protocol
The DALI protocol uses the bi-phase Manchester asynchronous serial data format. All the
bits of the frame are bi-phase encoded except the two stop bits.
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A forward frame consists of 19 bi-phase encoded bits: 1 start bit (logical ’1’), 1 address byte
and 1 data byte. The frame is terminated by 2 stop bits (idle). The stop bits do not contain
any change of phase.
A backward frame consists of 11 bi-phase encoded bits: 1 start bit (logical ’1’) and 1 data
byte. The frame is terminated by 2 stop bits (idle). The stop bits do not contain any change
of phase.
The transmission rate, expressed as a bandwidth, is specified at 1.2 kHz for the forward
channel and for the backward channel.
The settling time between two subsequent forward frames is 9.17 ms (minimum).
The settling time between forward and backward frames is between 2.92 ms and 9.17 ms. If
a backward frame has not been started after 9.17 ms, this is interpreted as "no answer".
In the event of code violation, the frame is ignored. After a code violation has occurred, the
system is ready again for data reception.
Figure 42. DALI standard frame
The transmission rate is about 1.2 kHz. The bi-phase bit period is 833.33 us ±10%.
A forward frame consists of 19 bi-phase encoded bits:
– 1 start bit (0->1: logical ’1’)
– 1 address byte (8-bit address)
– 1 data byte (8-bit data)
– 2 high level stop bits (no change of phase)
A backward frame consists of 11 bi-phase encoded bits:
– 1 start bit (0->1: logical ’1’)
– 1 data byte (8-bit data)
– 2 high level stop bits (no change of phase)
start bit
2T
a7
2T
a6
2T
a5
2T
start bit
address byte
a4
2T
2T
Logical ’1’
a3
2T
d7
2T
a2
2T
d6
2T
BACKWARD FRAME
FORWARD FRAME
a1
2T 2T
d5
2T
2T
BI-PHASE LEVELS
data byte
a0
d4
2T
2T
d7
d3
2T
2T
d6
d2
2T
2T
2T
d5
d1
2T 2T
Logical ’0’
data byte
2T
d4
d0
DALI communication module
2T
d3
stop bits
2T = 833.33 us ±10%
4T
2T
d2
2T
d1
2T
d0
stop bits
4T
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